Titre : | Optimizing clock resources in FPGAs (2016) |
Auteurs : | Colin O'Flynn, Auteur |
Type de document : | Article : texte imprimé |
Dans : | Circuit cellar (311, June 2016) |
Article en page(s) : | P. 54-59 |
Langues: | Américain |
Sujets : |
IESN Electronique ; Field-Programmable Gate Array ; Programmation |
Résumé : |
"This article is a case study of why you should pay attention to the underlying architecture your HDL code is running on. The use of the simple clock buffer is explored in the Spartan 6 FPGA, and a demonstration of where you might run into placement errors and how you can fix them is given. More generally, this explores the use of the FPGA Editor to get a feel for how your design is being implemented on the physical hardware." (Extrait de Circuit cellar n°311)
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Exemplaires (1)
Localisation | Section | Support | Cote de rangement | Statut | Disponibilité |
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Bibliothèque IESN | _Périodiques | Périodique | 62 CIR 311 | Consultation possible sur demande | Exclu du prêt |