| Titre : | Cache Coherence and the ACE Protocol : snooping and synching (2021) |
| Auteurs : | Nishant Mittal, Auteur |
| Type de document : | Article : texte imprimé |
| Dans : | Circuit cellar (375, October 2021) |
| Article en page(s) : | p. 36-40 |
| Langues: | Américain |
| Sujets : |
IESN Cache ; Electronique ; Mémoire vive ; Protocole ACE (électronique) ; RAM |
| Résumé : | "Snooping and Synching Cache coherency is a fundamental concept for processor-based systems. Nishant explains the basics of cache coherency and then explores how Arm’s ACE protocol ensures a more cache-friendly system design. Topics Covered How cache coherency worksHow Arm's ACE protocol worksWhat are the three methods of cache coherencyHow the ACE protocol worksHow AXI and ACE are different Tech Discussed Arm’s ACE protocolMOESI protocol Cache coherency has been a hot topic since the development of accelerated hardware and parallel processing. It’s been a key concept for performance hungry systems. In such performance-hungry hardware and software, we just cannot afford to do every read and write from the main memory." (Extrait de Circuit cellar n°375) |
Exemplaires (1)
| Localisation | Section | Support | Cote de rangement | Statut | Disponibilité |
|---|---|---|---|---|---|
| Bibliothèque IESN | _Périodiques | Périodique | 62 CIR 375 | Consultation possible sur demande | Exclu du prêt |
